Impact of buffering mechanism on SoFPGA ip router cost

In today\u27s world of advanced technology numerous applications are computational intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA, for future SoFPGA has been presented. The IP router is the heart of NoFPGA. The design cost of IPRouter Buffering, the most expensive building block, is evaluated based on two different implementation approaches. First, IPRouter buffering based on distributed memory. Second, IPRouter buffering based on Embedded Block RAMs. © 2006 IEEE