Graph sparsification approaches to scalable integrated circuit modeling and simulations

© 2014 IEEE. Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for verification of large IC designs. Post-layout SPICE-accurate simulation should be able to encapsulate multi-million or even multi-billion devices that are coupled through complex parasitics and become an essential procedure for verification of nowadays nano-scale IC designs. Although many efficient numerical methods have been developed and adopted in the state-of-the-art SPICE-accurate circuit simulators for solving large sparse matrices involved in IC simulations, existing simulators may not be capable of handling extremely large-scale post-layout ICs in that the computation and memory cost can increase exponentially with the increase of circuit sizes and parasitics components. This paper introduces our recent effort in developing \u27truly scalable\u27 SPICE-accurate nonlinear circuit simulation methods that can scale comfortably with extremely large-scale post-layout IC designs without sacrificing accuracy