A 54.2 μw 5 MSps 9-bit ultra-low energy analog-to-digital converter in 180 nm technology

This paper aims to address the growing need for ultra-low power analog-to-digital converters (ADC). For this purpose, we pushed the limitations of conventional successive approximation register ADCs through the use of deep voltage scaling, a novel iterative precharging scheme, and topological improvements over recent works. From the simulations results we achieve a figure of merit of 31 fJ per conversion step, with an 8.45 effective number of bits, working at 5 MSps