A model for copper electroplating of through-silicon vias (TSV) is proposed based on the suppressor adsorption/desorption mechanism, with special emphasis on the bottom-up filling of these structures. The proposed model is applicable for both 2-component (suppressor and accelerator) and 1-component (suppressor only) Cu plating chemistries. Numerical simulation was performed for the filling of 5 μm (diameter) × 40 μm (depth) vias. Simulated Cu profiles and the corresponding dependencies on additive concentration are confronted with existing experimental results.status: publishe
The desorption / adsorption of suppressor additive during Cu electroplating plays a critical role in...
Through silicon via (TSV) is a key technology for the future high density 3D packaging in microelect...
3D integration with TSVs(Through Silicon Via)is emerging as a promising technology for the next gene...
Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integ...
A method is introduced for Cu bottom-up filling at trenches with dimensions similar to those of thro...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next ge...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
In this work, the Cu electrodeposition was carried out for the filling of through silicon via (TSV) ...
Abstract Three-dimensional integration with through-silicon vias (TSVs) is a promising microelectron...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of ...
Studies of through-silicon vias (TSVs) have become important owing to the increasing demand for 3D p...
In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the ...
The 3D technology, in integrated circuit applications, refers to the stacking of chips on top of ea...
For 3D stacked flip chip packages, through silicon vias (TSVs) are employed as vertical interconnect...
The desorption / adsorption of suppressor additive during Cu electroplating plays a critical role in...
Through silicon via (TSV) is a key technology for the future high density 3D packaging in microelect...
3D integration with TSVs(Through Silicon Via)is emerging as a promising technology for the next gene...
Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integ...
A method is introduced for Cu bottom-up filling at trenches with dimensions similar to those of thro...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next ge...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
In this work, the Cu electrodeposition was carried out for the filling of through silicon via (TSV) ...
Abstract Three-dimensional integration with through-silicon vias (TSVs) is a promising microelectron...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of ...
Studies of through-silicon vias (TSVs) have become important owing to the increasing demand for 3D p...
In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the ...
The 3D technology, in integrated circuit applications, refers to the stacking of chips on top of ea...
For 3D stacked flip chip packages, through silicon vias (TSVs) are employed as vertical interconnect...
The desorption / adsorption of suppressor additive during Cu electroplating plays a critical role in...
Through silicon via (TSV) is a key technology for the future high density 3D packaging in microelect...
3D integration with TSVs(Through Silicon Via)is emerging as a promising technology for the next gene...