Applying Microarchitectural Prediction to Improve Performance and Security

Modern processors rely heavily on speculation to provide performance. Techniques such as branch prediction, caching, prefetching, memory dependence prediction etc. use features from recent program behavior to predict the near future, allowing remarkable improvement in performance and energy efficiency. Speculative execution use instruction caches (I-cache), branch target buffers (BTB) and Translation Look-aside Buffers (TLBs) to improve instruction fetch in front-end. The branch predictor speculates about future control flow while cache structures speculate about future data and instruction accesses. TLBs help minimize the need for costly page table-sourced translations by caching recently retrieved virtual-to-physical address. Due to timing and area constraints, the I-cache, BTB and TLBs must make efficient use of their limited capacities. Blocks in the I-cache or entries in the BTB/TLBs that have low potential for reuse should be replaced by more useful blocks/entries. In this dissertation we will show that previous predictive replacement policies are not sufficient for instruction stream. We first explain our work on predictive replacement policies based on reuse prediction that can be applied to both the I-cache and BTB. We will then investigate the effectiveness of predictive policies for TLBs. After showing how prediction can improve microarchitecute through predictive policies for front-end we will explain the security challenges that modern processors face due to speculation. We will see that speculative attacks can leak information through micro-architectural side-channels that are not bugs, but in fact lie at the foundation of optimization. Solutions can only be practical if they provide a useful trade-off between security and performance. We show that microarchitectural prediction can be applied to processors to improve performance and security. Therefore, the central thesis of this dissertation is this: Despite the complexity of modern superscaler processors and speculative execution attacks, future microarchitectural prediction can improve both performance and security