Reconfigurable ALU Array (RAA) architectures - representing a popular class of Coarse-grained Reconfigurable Architectures - are gaining in popularity especially for media applications due to their flexibility, regularity, and efficiency. In such architectures, memory is critical not only for configuration data but also for the heavy data traffic required by the application. In this paper, we offer a scheme for system designers to quickly estimate the performance of media applications on RAA architectures. Our experimental results demonstrate the flexibility of our memory architecture evaluation scheme as well as the varying effects of the memory architectures on the application performance
Abstract — Mapping applications onto reconfigurable architectures can be done in many different ways...
Memory performance becomes a dominant factor for today’s microprocessor applications. In this paper,...
This thesis investigates the impact of the global and local register file architecture on a reconfig...
Reconfigurable ALU Array (RAA) architectures - representing a popular class of Coarse-grained Reconf...
We describe our experience using reconfigurable architectures to develop an understanding of an appl...
With the increasing demand for flexible yet highly efficient architecture platforms for media applic...
Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10...
Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-...
Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program...
Workloads on general-purpose computing systems have changed dramatically over the past few years, wi...
This Thesis focuses on the acceleration of different applications using a run-time reconfigurable ar...
Abstract — Recent technology development enables differ-entiation not only in application specific c...
One of the challenges for characterizing and modeling realistic multimedia applications is the lack ...
Hierarchical memory is a cornerstone of modern hardware design because it provides high memory perfo...
This paper aims to provide a quantitative understanding of the performance of image and video proces...
Abstract — Mapping applications onto reconfigurable architectures can be done in many different ways...
Memory performance becomes a dominant factor for today’s microprocessor applications. In this paper,...
This thesis investigates the impact of the global and local register file architecture on a reconfig...
Reconfigurable ALU Array (RAA) architectures - representing a popular class of Coarse-grained Reconf...
We describe our experience using reconfigurable architectures to develop an understanding of an appl...
With the increasing demand for flexible yet highly efficient architecture platforms for media applic...
Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10...
Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10-...
Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program...
Workloads on general-purpose computing systems have changed dramatically over the past few years, wi...
This Thesis focuses on the acceleration of different applications using a run-time reconfigurable ar...
Abstract — Recent technology development enables differ-entiation not only in application specific c...
One of the challenges for characterizing and modeling realistic multimedia applications is the lack ...
Hierarchical memory is a cornerstone of modern hardware design because it provides high memory perfo...
This paper aims to provide a quantitative understanding of the performance of image and video proces...
Abstract — Mapping applications onto reconfigurable architectures can be done in many different ways...
Memory performance becomes a dominant factor for today’s microprocessor applications. In this paper,...
This thesis investigates the impact of the global and local register file architecture on a reconfig...