Calculation of Power-Supply-Induced Jitter at a 3-D IC channel including ESD Protection Circuits
- Park, Eunkyeong
- Kim, Jingook
- Lee, Jongjoo
- Park, Youngwoo
Publication date
August 2015
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
The step response of a single ended output driver with silicon interposer channel is derived including the parasitics of ESD protection circuits. The probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated. With changing the frequency of supply voltage fluctuations, the effect of ESD parasitics on the output jitter is calculated and compared
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