We propose a low-overhead technique, Token-Based Adaptive Power Gating (TAP), to power gate an actively executing out-of-order core during memory accesses. TAP tracks every system memory request, providing a lower-bound estimate for the response time. TAP also tracks the state of every power-gateable core in the system, to provide minimal latency wake-up modes to cores such that voltage noise safety margins are not violated. A power-gating switch that utilizes TAP can deterministically power gate its core with energy savings up to 22.39% and no performance hit
A dynamically-controlled power-gated (DCPG) FPGA ar-chitecture has recently been proposed to reduce ...
Power gating is one of the most effective solutions available to reduce leakage power. However, powe...
Abstract- The large magnitude of supply/ground bounces, which arise from power mode transitions in p...
Among power dissipation components, leakage power has become more dominant with each successive tech...
In mobile systems, the problems of short battery life and increased temperature are exacerbated by w...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
International audiencePower gating is an increasingly important actuation knob in chip-level dynamic...
With the widespread adoption of GPGPUs in varied ap-plication domains, new opportunities open up to ...
We introduce and analyze the ground bounce due to power mode transition in power gating structures. ...
[[abstract]]Power gating has been a very effective way to reduce leakage power. One important design...
Power gating is an effective method to reduce leakage power during the circuit sleep mode; however, ...
High performance and computational capability in the current generation processors are made possible...
Leakage power is a growing concern in modern technology nodes. In some current and emerging applicat...
As the CMOS technology scales down, the cost of fabricating an integrated circuit becomes more expen...
Abstract—Power gating is effective for reducing standby leakage power asmulti-thresholdCMOS (MTCMOS)...
A dynamically-controlled power-gated (DCPG) FPGA ar-chitecture has recently been proposed to reduce ...
Power gating is one of the most effective solutions available to reduce leakage power. However, powe...
Abstract- The large magnitude of supply/ground bounces, which arise from power mode transitions in p...
Among power dissipation components, leakage power has become more dominant with each successive tech...
In mobile systems, the problems of short battery life and increased temperature are exacerbated by w...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
International audiencePower gating is an increasingly important actuation knob in chip-level dynamic...
With the widespread adoption of GPGPUs in varied ap-plication domains, new opportunities open up to ...
We introduce and analyze the ground bounce due to power mode transition in power gating structures. ...
[[abstract]]Power gating has been a very effective way to reduce leakage power. One important design...
Power gating is an effective method to reduce leakage power during the circuit sleep mode; however, ...
High performance and computational capability in the current generation processors are made possible...
Leakage power is a growing concern in modern technology nodes. In some current and emerging applicat...
As the CMOS technology scales down, the cost of fabricating an integrated circuit becomes more expen...
Abstract—Power gating is effective for reducing standby leakage power asmulti-thresholdCMOS (MTCMOS)...
A dynamically-controlled power-gated (DCPG) FPGA ar-chitecture has recently been proposed to reduce ...
Power gating is one of the most effective solutions available to reduce leakage power. However, powe...
Abstract- The large magnitude of supply/ground bounces, which arise from power mode transitions in p...