Techniques for Improving Coarse-Grained Reconfigurable Architectures

This paper presents various novel techniques for improving coarse-grained reconfigurable architectures. Specifically, it presents techniques for supporting IEEE single precision floating-point standard, efficient handling of loop-carried dependency with variable-length FIFOs, efficient mapping of control flows, and sharing data with a host processor for transparent binary acceleration. Experiments with benchmark examples demonstrate the effectiveness of the proposed techniques