Architecture exploration of standard-cell and FPGA-overlay CGRAs using the open-source CGRA-ME framework

We describe an open-source software framework, CGRA-ME, for the modeling and exploration of coarse-grained reconfigurable architectures (CGRAs). CGRAs are programmable hardware devices having large ALU-like logic blocks, and datapath bus-style interconnect. CGRAs are positioned between fine-grained FPGAs and standard-cell ASICs on the spectrum of programmability – they are less flexible than FPGAs, yet are more flexible than ASICs. With CGRA-ME, an architect can describe a CGRA architecture in an XML-based language. The framework also allows the architect to map benchmarks onto the architecture and provides automatic generation of Verilog RTL for the modeled architecture. This allows the architect to simulate for verification purposes, and perform synthesis to either an ASIC or FPGA-overlay implementation of the CGRA, assessing performance, area, and power consumption. In an experimental study, we use CGRA-ME to model, map benchmarks onto, and evaluate several variants of a widely known CGRA [24], considering both standard-cell and FPGA-overlay physical realizations of the CGRA