Enhanced Contribution of Edge Tunneling Effect to Current-Voltage Characteristics of Al/Si and Al/Graphene/Si Junctions with Lateral Size Scaling

The origin of Fermi-level pinning in a Schottky junction is known to be the electric dipole layer associated with the localized surface states on the semiconductor substrate. The influence of this electric dipole layer affecting the electrostatic potential pr ofile across the interface is notably reduced when the junction size becomes small [1,2]. In this study, it is demonstrated exp erimentally that the effective Schottky barriers of Al/Si and Al/Graphene/Si junctions decrease with the lateral width of junctio n decreasing. From the finite-element electrostatic modeling to obtain the energy band profile across the junction, the current-voltage (I-V) characteristics are found to be dominated more and more by the tunneling of charge carriers around the edges as the lateral size of junction becomes smaller. In case of the Al/Graphene/Si junction, the non-ideal I-V curve for forward bias was also observed, which is considered to be due to the recombination current in the graphene layer [3]. It is believed that our work can provide a physically-reasonable clue for understanding the drastic size-dependent variation of I-V characteristics in metal/Si junctions, the rectifying behavior of large-area junction [2] and the ohmic-like behavior of small-area one [4, 5])