Lower power by voltage stacking:a fine-grained system design approach

\u3cp\u3eStacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and V\u3csub\u3eDD\u3c/sub\u3e, and the memory on top of it between V\u3csub\u3eDD\u3c/sub\u3e and 2V\u3csub\u3eDD\u3c/sub\u3e, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in stacked mode of 96%.\u3c/p\u3