On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 mu m CMOS logic technology 

[[abstract]]This paper describes a leading-edge 0.13 mum low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I-off) and gate delay (T-d) performance at operation voltages (V-CC) 1.5 V and 1.2 V, devices with 0.11 mum nominal gate length (L-g_nom)and various gate-oxide thickness (T-ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Angstrom in order to keep acceptable off-state power consumption at V-CC = 1. 2 V. Specifically, two different device designs are introduced here. One design named LP (T-ox = 26 Angstrom) is targeted for V-CC = 1.5 V with worst case I-off < 10 pA/mum and nominal gate delay 24 ps/gate. Another design, named LP1 (T-ox = 22 Angstrom) is targeted for V-CC = 1.2 V with worst case I-off < 20 pA/mum and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 muA/mum nominal drive currents at V-CC for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 mum(2) cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T-ox = 22 Angstrom) demonstrate that gate oxide reliability far exceeds 10 years is achieved for both n/pMOSFETs at T = 125 degreesC and V-CC = 1.5 V.[[note]]SC