An analysis of substrate effects on transmission-lines for millimeter-wave CMOS RFIC applications

[[abstract]]A set of transmission lines (TLs) for millimeter-wave (MMW) CMOS RFIC applications was implemented in a standard 0.18 pun CMOS technology and then postprocessed by CMOS-compatible inductively-coupled plasma (ICP) etching, which removed the silicon underneath the TLs completely. TL parameters such as characteristic impedance Zc, attenuation constant alpha, phase constant beta, effective permittivity epsilon(eff) minimum noise figure (NFmin), parallel capacitance/conductance C/G, and series inductance/resistance L/R, as a function of frequency were extracted. It was found that alpha, epsilon(eff), NFmiv C, and G were greatly improved after silicon removal. The state-of-the-art performances of the on-chip TLs-on-air suggest that the), are very suitable for application to realize ultralow-noise MMW CMOS RFICs, Besides, the CMOS-compatible backside ICP etching technique is very promising for MMW system-on-a-chip applications. (c) 2007 Wiley Periodicals, Inc.[[note]]SC