Design and implementation of A 24-/60-GHz dual-band monopole meander-line planar CMOS antenna

[[abstract]]This article describes the design and implementation of a monolithic 24/60-GHz dual-band millimeter- wave planar CMOS antenna.A finite element method-based 3D full-wave electromagnetic solver, high-frequency structure simulator, is used to simulate and optimize the performance of the antenna. The feeding network adopts the coplanar waveguide (CPW) structure, so the on-chip antenna can be flip-chip-bonded to a CPW RO4003 conversion board for complete radiation-pattern measurement. The main structure uses meander-line to save chip area. Dual-band operation is achieved by providing two major current paths for radiation. The measured input voltage standing wave ratio of the on-chip dual-band antenna is smaller than 2 for frequencies 1025.7 and 58.466.6 GHz. The measured maximum power gain is -7 dB at 60 GHz, one of the highest power gains ever reported for a CMOS antenna at 60 GHz. The chip area is only 1 X 0.75 mm2, i.e., 0.75 mm2, excluding the periphery conductor and the dummy metals for metal density requirement. (C) 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:17311737, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26916[[note]]SC