3-11 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

[[abstract]]A CMOS distributed amplifier (DA) with. at and low noise figure (NF), and. at and high gain (S(21)) is demonstrated. A. at and low NF was achieved by adopting a RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF response. Besides, flat and high S(21) was achieved using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and a splitting-load inductive-peaking inverter stage. In the high-gain (HG) mode, the DA consumed 27.6 mW and achieved S(21) of 17.5 +/- 1.23 dB with an average NF of 3.24 dB over the 3 - 10 GHz band, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. The measured IIP3 was 2.1 dBm (at 8 GHz). In the low-gain (LG) mode, the DA achieved S(21) of 10.74 +/- 1.2 dB and an average NF of 4.67 dB with a low power dissipation of 9 mW.[[note]]SC