Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems

[[abstract]]A 3-10 GHz CMOS distributed amplifier (DA) with. at and low noise figure (NF) and. at and high power gain (S(21)) is demonstrated. A. at and low NF was achieved by adopting an RL terminating network for the gate transmission line, and a slightly under- damped Q-factor for the second- order NF frequency response. Besides, an. at and high S(21) was achieved by using the proposed cascade gain cell, which constitutes a cascode- stage with a low- Q RLC load and an inductive-peaking common- source stage. In the high-gain mode, the DA consumed 37.8 mW and achieved a. at and high S(21) of 20.47 +/- 0.72 dB with an average NF of 3.29 dB over the 3-10 GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or low- noise amplifier. In the low- gain mode, the DA achieved S(21) of 11.03 +/- 0.98 dB and an average NF of 4.25 dB with a power dissipation (P(D)) of 6.86 mW, the lowest P(D) ever reported for a CMOS UWB DA or LNA with an average S(21) of greater than 10 dB.[[note]]SC