International audienceThis paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approac
Abstract. As System on a Chip (SoC) testing faces new challenges, some new test architectures must b...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
A new core test wrapper design approach is proposed which transports streaming test data, for exampl...
This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE ...
This survey introduces into the common practices, current challenges and advanced techniques of high...
Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 S...
The main objective of core-based IC design is improvement of design efficiency and time-to-market. I...
As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. ...
Large single-die system chips are designed in a modular fashion, including and reusing pre-designed ...
Abstract—The increasing importance of embedded software has produced a shift in the testing activiti...
[[abstract]]©2001 CIEE-With the advent of deep-submicron technologies, system-on-chip (SOC) designs,...
Increasing complexity of circuit boards and surface mount technology has made it difficult to test t...
This document briefly describes the upcoming standard IEEE 1500 [1], titled "Standard Testabili...
Traditional test and measurement equipment that relies on connecting external probes is no longer p...
As the size and complexity of SoC design grow, it is common to establish a scalable and reusable ver...
Abstract. As System on a Chip (SoC) testing faces new challenges, some new test architectures must b...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
A new core test wrapper design approach is proposed which transports streaming test data, for exampl...
This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE ...
This survey introduces into the common practices, current challenges and advanced techniques of high...
Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 S...
The main objective of core-based IC design is improvement of design efficiency and time-to-market. I...
As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. ...
Large single-die system chips are designed in a modular fashion, including and reusing pre-designed ...
Abstract—The increasing importance of embedded software has produced a shift in the testing activiti...
[[abstract]]©2001 CIEE-With the advent of deep-submicron technologies, system-on-chip (SOC) designs,...
Increasing complexity of circuit boards and surface mount technology has made it difficult to test t...
This document briefly describes the upcoming standard IEEE 1500 [1], titled "Standard Testabili...
Traditional test and measurement equipment that relies on connecting external probes is no longer p...
As the size and complexity of SoC design grow, it is common to establish a scalable and reusable ver...
Abstract. As System on a Chip (SoC) testing faces new challenges, some new test architectures must b...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
A new core test wrapper design approach is proposed which transports streaming test data, for exampl...