Hardware Design and Implementation of a Discrete Wavelet Transform based Image Compression System for Optical Remote Sensing

為了人造衛星上進行的光學遙測任務，美國太空資料系統諮詢委員會(Consultative Committee for Space Data Systems，CCSDS)發展出一資料壓縮標準規範，目的在於將拍攝到的衛星影像進行壓縮且可與地面接收站進行即時傳輸。其演算法是以JPEG 2000為基礎所改良，由於是專門針對光學遙測任務所用，其演算法致力於壓縮效能與影像品質的最佳平衡，主要分成離散小波轉換(Discrete Wavelet Transform, DWT)與Bit-Plane Encoder(BPE)兩大部分。前者目的在於去除資料間的相關性(decorrelation)，而BPE則是將DWT所獲得的頻譜係數進行壓縮編碼，並提供資料率以及影像品質調整的機制。 本論文即針對此演算法發展出了一套影像資料壓縮系統的硬體架構，並將DWT部分以可程式邏輯閘陣列(FPGA)進行硬體實現。根據CCSDS規範，其影像壓縮格式可分為失真(lossy)與無失真(lossless)兩種模式，其中失真模式是使用浮點數型態(floating type)的小波轉換，硬體架構上採用9/7濾波器型式的架構；而無失真模式是使用整數型態(integer type)的小波轉換，硬體架構上則是採用上提式架構，兩者皆是進行3 levels的離散小波轉換。本論文針對此兩種型態各別設計出完整的硬體電路架構，可支援不同的輸入影像寬度，且利用定點分析模擬結果來制定各個獨立模組中的word length，並以pipeline、folding等技術來達到硬體加速及優化硬體使用率。在記憶體部分則使用到ping-pong buffer之技術和精確定點分析來將記憶體用量節省到最少，以利未來設計上的擴充性。整個硬體電路經FPGA實現後最大工作頻率可達到88.51MHZ，在最大輸入影像寬度為8192 pixels的情況下，每秒可處理一萬條以上的lines。而本論文之電路設計中也包含了遙測功能以應付太空任務所需，其硬體是以一UART之IP core實現，可支援各種指令參數輸入和FPGA運作時的即時狀態回傳，方便使用者在資料錯誤時可進行較簡單的偵錯。 本論文中的最終硬體驗證是採用軟硬體協同的方式，將透過FPGA運算出的DWT係數輸入至PC端，再以CCSDS規範的BPE軟體進行壓縮及還原。驗證結果在壓縮比為8時，以CCSDS提供的8張衛星影像做為測試樣本經還原後平均PSNR值可達到48dB。 除了DWT部分的硬體實現之外，本論文也依據CCSDS之演算法架構規劃了初步的BPE所需硬體模組和系統時序，在處理bit plane時使用了平行處理架構以及在各個模組間插入了pipeline來大幅減少硬體資源消耗。For the optical remote sensing task on the satellite, Consultative Committee for Space Data Systems (CCSDS) has developed a data compression standard. Its purpose is compressing the satellite imagery and transmitting it to the ground earth station in real time. The algorithm is based on JPEG 2000. It is devoted to the balance between compression rate and image quality. It consists of two parts: Discrete Wavelet Transform(DWT) and Bit-Plane Encoder(BPE). The purpose of DWT is decorrelation. Then BPE then encodes the coefficients decomposed by DWT and offers the function of data rate control and image quality adjustment. In this thesis, we present a hardware design of image compression system based on CCSDS algorithm and implement it in a FPGA device. According to CCSDS standard, the compression algorithm can be classified into two categories: lossy and lossless. The former adopts the floating type DWT and can be implemented by using a 9/7 filter architecture. The latter adopts the integer type DWT and can be implemented by using a lifting based architecture. Both of them perform a 2-dimentional 3-level DWT decomposition. This thesis presents a complete DWT hardware architecture supporting these types. It also supports a push-broom style input scanning with adaptive image width settings. Fixed point simulations are first conducted to determine the word length of each individual hardware module. Various hardware design techniques such as pipeline and folding are employed to improve the clock frequency and to optimize the hardware utilization ratio. In addition, a ping-pong buffer strategy is employed to minimize the memory usage for the future design expansion. The design module is implemented in a FPGA device with a maximum clock frequency of 88.51 MHz. The system’s throughput rate can reach more than 10,000 scanning lines per second when the width of input image is under 8192 pixels per line. The design is also equipped with a telematics interface implemented by using a UART IP core. The telematics interface enables system setting and debugging. The DWT design is verified based on the concept of hardware/software co-verification. We use the BPE software based on the CCSDS standard to encode and decode the DWT coefficients computed by a FPGA device and observe the PSNR value. The experimental results indicate the average PSNR value of 8 test images provided by CCSDS is 48 dB when the compression ratio is 8. In addition to the DWT module design, we have also complete a preliminary architecture and system timing of BPE design based on CCSDS standard. Parallel architecture is utilized in a bit plane and pipeline is utilized to reduce the resource consumption greatly.摘要 i Abstract iii 目錄 v 圖目錄 vii 表目錄 ix 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機及目標 2 1.3 CCSDS演算法與JPEG2000之比較 3 1.4 論文架構 4 第二章 光學影像資料壓縮系統 5 2.1 小波轉換原理介紹 5 2.2 上提式小波轉換 7 2.3 Bit-Plane Encoder演算法架構 11 2.4 文獻回顧 17 2.5 硬體設計挑戰 21 第三章 9/7濾波器架構與上提式架構之小波轉換電路設計 23 3.1 壓縮比(compression ratio)與PSNR值模擬及定點分析 24 3.1.1 浮點數型態(Floating Type)小波轉換定點分析 25 3.1.2 整數型態(Integer Type)小波轉換定點分析 27 3.2 系統方塊圖及模組IO 29 3.3 硬體時序圖規劃 31 3.3.1 浮點數型態小波轉換硬體時序 31 3.3.2 整數型態小波轉換硬體時序 34 3.3.3 小波轉換硬體電路整體時序 36 3.4 記憶體配置規劃 37 3.5 DWT硬體電路設計 40 3.5.1 浮點數型態小波轉換電路架構 40 3.5.2 整數型態小波轉換電路架構 42 3.6 Telematics Interface 44 3.7 BPE硬體模組規劃 47 第四章 小波轉換硬體電路於FPGA之設計與實現 51 4.1 電路模擬與bit true驗證 52 4.1.1 電路波形圖觀察 52 4.1.2 Bit true驗證 53 4.2 RTL電路合成結果 54 4.3 FPGA實現與驗證 57 4.3.1 FPGA驗證系統 57 4.3.2 目標需求三種影像寬度驗證 60 4.3.3 DWT與BPE整合之PSNR值驗證 62 4.3.4 Header資訊產生 63 第五章 結論與展望 64 參考文獻 6