CBCA: balance cache checkpointing for superscalar processors

The reliability of future general-purpose processors (GPPs) is threatened by a combination of factors like shrinking transistor size, higher clock rates, and reduced supply voltages. It is predicted that the occurrence of soft errors will dramatically increase as these trends continue. It is necessary that the processors be covered from the effects of transient faults with predictable minimal impact on performance. Such a predictable impact would allow the processor to be employed in real-time applications. In this thesis, we propose a superscalar architecture based on checkpointing buddy cache architecture. This architecture keeps the execution of tasks free from soft errors by detecting the fault in the execution state and resetting the state of the processor to last known fault free state. Our scheme minimizes the overhead of checkpointing by eliminating the unnecessary checkpoints. We added checkpointing buddy cache (CBC), a small fully associative cache, which works in parallel with the data cache. Whenever there is a need for replacing a dirty line from the data cache, then instead of writing it to main memory and taking a checkpoint, it is written to CBC. The checkpoint is taken when the CBC is filled with dirty lines. The results show that the number of checkpoints required for the checkpointing buddy cache architecture (CBCA) is 10% to 80% less than the conventional cache checkpointing architecture. The cache miss rate for our scheme is also reduced up to 26% as compared to base processor. The number of checkpoints and miss rate were found to be decreasing with the increase in the size of CBC. However, the access time for CBC of size 32 lines was found to be greater than the data cache, thus making CBC of size greater than 32 impractical. CBCA provides fault tolerant mechanism to protect the processor against soft errors, while providing task execution time similar to base processor