Reliability and Integration of GaN Power Devices and Circuits on GaN-on-SOI

Power transistors on GaN-on-Si are very promising for power switching applications. In the past two decades, great efforts have been paid to promote epitaxy quality of GaN on Si, decrease vertical leakage current, achieve real enhancement device, and suppress device dispersion. Fortunately, those problems have sequentially been solved and the commercialization is upcoming. To further explore the potential of GaN, some new concepts like monolithic integration of power systems on the same chip has been proposed to reduce the parasitic inductance and die size. Compared with the traditional Si vertical power devices, the GaN devices with a lateral configuration is much more convenient to achieve monolithic integration. However, the effective isolation of the GaN devices is quite challenging because those devices share a common conductive Si substrates. This Ph.D topic will focus on using GaN-on-SOI combined with trench isolation to achieve monolithic integration. Some issues need to be solved for this target, including a) investigation of the traps, vertical leakage mechanism, and reliability of the GaN buffer on SOI; b) evaluation of the effectiveness of the isolation by the trench and SiO2 layer; c) probing the increase of thermal resistance induced by the oxide layer; d) evaluation of the reliability of each discrete device; e) measurement of the switching performance of the monolithic integrated half bridge.status: accepte