A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gbps ultra-wideband (UWB) transceiver fabricated in 28nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops (PLLs), one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing (FBB) is used to control a back-bias-controlled oscillator (BBCO) and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature (PVT) variations, including skewed process corners. The CR occupies a silicon area of 0.043mm², locks in less than 1.1μs, generates an RMS long-term jitter of 6.5ps, and consumes 1.034mW while in-lock. This results in an energy value of 0.414pJ/cycle and a jitter FoM of -224dB