This paper presents a completely systematic design procedure for asynchronous controllers.The initial step is the construction of a signal transition graph (STG, an interpreted Petri net) ofthe dialog between data path and controller: a formal representation without reference to timeor internal states. To implement concurrently operating control structures, and also to reducedesign effort and circuit cost, this STG can be decomposed into overlapping subnets. A univer-sal initial solution is then obtained by algorithmically constructing a primitive flow table fromeach component net. This step links the procedure to classical asynchronous design, in particu-lar to its proven optimization methods, without restricting the set of solutions. In c...
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data co...
Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization ...
This paper shows a novel prototyping technique for concurrent control systems described by interpret...
The synthesis of asynchronous circuits is inherently complex for two different aspects. Firstly, the...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
Abstract: Design, validation and synthesis of digital systems, are currently done with the aid of CA...
A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based ...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
This paper presents a new methodology to automatically synthesize asynchronous circuits from descrip...
International audienceCommunicating Hardware Processes (CHP) is a CSP-like language for describing a...
Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed m...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal...
Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed ...
A synthesis technique for asynchronous sequential control circuits from a high level specification, ...
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data co...
Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization ...
This paper shows a novel prototyping technique for concurrent control systems described by interpret...
The synthesis of asynchronous circuits is inherently complex for two different aspects. Firstly, the...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
Abstract: Design, validation and synthesis of digital systems, are currently done with the aid of CA...
A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based ...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
This paper presents a new methodology to automatically synthesize asynchronous circuits from descrip...
International audienceCommunicating Hardware Processes (CHP) is a CSP-like language for describing a...
Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed m...
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous ci...
Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal...
Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed ...
A synthesis technique for asynchronous sequential control circuits from a high level specification, ...
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data co...
Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization ...
This paper shows a novel prototyping technique for concurrent control systems described by interpret...