A methodology for characterizing and introducing MOSFET imperfections in analog top-down synthesis and bottom-up validation

State-of-the art electronic systems include ever more features and gather mixed-signal subsystems, possibly from different physical domains. At the same time, cost and development time are reduced; stressing the need for an efficient design flow for fast and reliable design. The present thesis contributes to the construction of an improved design flow supported by mixed-signal hardware description languages (HDL-AMS). In a hierarchical view, the electronic systems are recursively divided into subsystems, down to basic cells and transistor level. The typical design flow results of a top-down synthesis, from the system specifications to the physical realizations, and of a bottom-up validation, from the test of the basic cells up to the test of the system. To improve the link between the technological level and the basic cells, we develop a measurement-based analog ID card which aims to optimize the analog performance and the reliability at high temperature by enabling the choice of optimal process (bulk vs. partially-depleted silicon-on-insulator (SOI) vs. fully-depleted SOI), optimal devices (e.g. multi-threshold voltages process) and optimal bias (weak vs. moderate vs. strong inversion). In the present thesis, we deal with the following analog performance parameters: gain, gain-bandwidth product, MOSFET mismatch in weak inversion and harmonic distortion of MOSFETs in triode regime. We show that SOI transistors are still advantageous over bulk in deep-submicron CMOS technologies and that short-channel SOI transistors can safely be used for mixed-signal operation up to 250°C. The analog ID card can be included in the design flow supported by HDL-AMS. Behavioral models for the basic cells are developed using such languages and further assembled into a ÄÓ modulator with continuous-time integrators as it is a good candidate for low-power consumption and operation at high temperature. The related design issues are assessed using the behavioral models and a design optimization method is presented for a key building block, an active RC integrator with passive resistors.(FSA 3)--UCL, 200