Source/Drain Engineered Ultra Low Power Analog/RF UTBB MOSFETs

We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (gm/Ids) and cut-off frequency (fT) product i.e. gmfT/Ids as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve gmfT/Ids, intrinsic voltage gain (AVO), cut-off frequency (fT) and linearity (VIP3) with downscaling