Add to ORKGA novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. As it will be shown, this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and raising time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations
This paper investigates the capability of an architecture with digitally controllable gain and power...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on...
The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell t...
Abstract In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit ...
With the increase in device integration level and the growth in complexity of Integrated circuits, s...
Motivated by emerging battery operated applications that demand intensive computation in portable en...
As technology advances, the rise in electronic products such as mobile phone, tablets and other hand...
Abstract: A Low-Voltage Low-Dropout(LDO) Voltage Regulator that can operate with a very small Input–...
Abstract—Motivated by emerging battery-operated applica-tions that demand intensive computation in p...
Power consumption is the bottleneck of system performance. Power reduction has become an important i...
In this paper a modified Constant Delay Logic is been proposed to provide improved performance. Cont...
Nowadays, state-of-the-art electronic devices are calling for high-speed and low-power subsystems t...
In this paper, design methodology of area-efficient and low-quiescent-current low-dropout regulators...
We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. ...
This paper investigates the capability of an architecture with digitally controllable gain and power...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on...
The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell t...
Abstract In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit ...
With the increase in device integration level and the growth in complexity of Integrated circuits, s...
Motivated by emerging battery operated applications that demand intensive computation in portable en...
As technology advances, the rise in electronic products such as mobile phone, tablets and other hand...
Abstract: A Low-Voltage Low-Dropout(LDO) Voltage Regulator that can operate with a very small Input–...
Abstract—Motivated by emerging battery-operated applica-tions that demand intensive computation in p...
Power consumption is the bottleneck of system performance. Power reduction has become an important i...
In this paper a modified Constant Delay Logic is been proposed to provide improved performance. Cont...
Nowadays, state-of-the-art electronic devices are calling for high-speed and low-power subsystems t...
In this paper, design methodology of area-efficient and low-quiescent-current low-dropout regulators...
We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. ...
This paper investigates the capability of an architecture with digitally controllable gain and power...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on...