Add to ORKGIn this work, we experimentally investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Both n- and p-type GP configurations are considered. Next, we demonstrate that application of asymmetric double-gate regime allows for the improvement of analog FoM in UTBB SOI MOSFETs with GP
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
Traditional scaling methodology which utilizes channel doping, shallow junctions, etc. is no longer ...
Abstract—The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mo...
International audienceFor the first time, the investigation and fabrication of a high-voltage MOSFET...
This work details the harmful effect of parasitic resistances and capacitances on RF figures of meri...
International audienceFor the first time, the investigation and fabrication of a high-voltage MOSFET...
Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the pot...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
Traditional scaling methodology which utilizes channel doping, shallow junctions, etc. is no longer ...
Abstract—The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mo...
International audienceFor the first time, the investigation and fabrication of a high-voltage MOSFET...
This work details the harmful effect of parasitic resistances and capacitances on RF figures of meri...
International audienceFor the first time, the investigation and fabrication of a high-voltage MOSFET...
Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the pot...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
International audienceFor the first time, the investigation of a high-voltage MOSFET (HVMOS) in Ultr...