Pushing ultra-low-power digital circuits into the nanometer era

Over the last decade, ultra-low-power (ULP) design of integrated circuits has become a vibrant research field for emerging applications such as sensor networks, biomedical devices or RFID tags. ULP circuits need to operate for a long time on tiny batteries, with minute energy consumption. Thanks to their low computational load, energy consumption can be minimized by scaling the supply voltage Vdd and the clock frequency fclk to the so-called minimum-energy point, which balances dynamic energy due to capacitance switching and static energy due to leakage currents. This often occurs for Vdd values below 0.4V, which leads to subthreshold operation. At the same time, Moore's-law-driven technology scaling leads to nanoscale CMOS processes with reduced die area and circuit capacitances. However, their severe drawbacks such as high leakage currents and device variability are magnified in subthreshold circuits because of low fclk and Vdd, respectively. This leads to the main questions of this dissertation: - What is the impact of nanometer technology scaling on subthreshold circuits ? - How to benefit from the die area reduction while keeping robustness and energy consumption under control ? To answer first question, we propose an analysis framework of energy efficiency in frequency/voltage-scaled digital circuits. Using this framework, we report three major issues in nanometer subthreshold circuits that we then try to fix to answer the second question. First, minimum-energy level increases when reaching 45nm node. We propose an optimum MOSFET selection in standard nanometer bulk technology leading to 40% energy saving, while we show that fully-depleted SOI technology can bring up to 60% saving. Second, practical energy at low throughputs becomes much higher than minimum-energy level. We propose an appropriated technology selection at 45nm node with adaptive reverse body biasing and an engineered power switch, to make practical energy meet the minimum-energy level. Finally, high-temperature operation (> 150°C) dramatically increases energy consumption through leakage currents. We propose a novel ULP logic style that reduces leakage currents by three orders of magnitude at the expense of circuit delay. It can be used to build high-temperature ULP circuits in standard SOI technology.(FSA 3) -- UCL, 200