A modified gm/ID design methodology for deeply scaled CMOS technologies

This paper presents an updated version of the gm/ID-based sizing methodology for advanced short-channel CMOS technologies. The objective of this technique is to quickly and accurately size any linear analog circuit, top–down, from some required specifications and evaluate the remaining ones. A database describing the underlying MOS technology is taken as input of the sizing script, making the sizing process technology and corner independent. An advanced CMOS technology is analyzed, underlining the limitations of the original gm/ID methodology and its past improvements, then the proposed methodology is described in detail and tested successfully on a double stage amplifier, using two different CMOS technologies in all process-voltage-temperature corners