In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-c...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
In this work, we experimentally investigate the effect of ground plane (GP) on analog figures of mer...
Traditional scaling methodology which utilizes channel doping, shallow junctions, etc. is no longer ...
This work investigates the simultaneous electrostatic improvement and performance enhancement of UTB...
Abstract—The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mo...
Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the pot...
Figures-of-merit of non-standard channel engineered devices are presented. We put emphasis on effect...
International audienceA promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28 n...
International audienceA promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28 n...
This work presents a systematic comparative study of the influence of various process options on the...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...
In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultr...
In this work, we experimentally investigate the effect of ground plane (GP) on analog figures of mer...
Traditional scaling methodology which utilizes channel doping, shallow junctions, etc. is no longer ...
This work investigates the simultaneous electrostatic improvement and performance enhancement of UTB...
Abstract—The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mo...
Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the pot...
Figures-of-merit of non-standard channel engineered devices are presented. We put emphasis on effect...
International audienceA promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28 n...
International audienceA promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28 n...
This work presents a systematic comparative study of the influence of various process options on the...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX ...
We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX...