A Design Methodology for Temperature Variation Insensitive Low Power Circuits

Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. Circuits display temperature variation insensitive delay characteristics when operated at a supply voltage 45% to 53% lower than the nominal supply voltage (V DD = 1.8V) in a 180nm CMOS technology. Integrated circuits operating at scaled supply voltages consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive in low power applications with relaxed speed requirements. The energy, delay, and energy-delay product (EDP) are compared at the supply voltages that yield temperature variation insensitive circuit performance and minimum energy-delay product. Results indicate that low-power integrated circuits can also be made insensitive to temperature fluctuations with a modest amount of increase in energy-delay product. Copyright 2006 ACM