The Clos-network is widely recognized as a scalable architecture for high-performance switches and routers. One of the key challenges in designing a Clos-network switch for a high-speed environment is the design of the dispatching/scheduling so as to be efficient for a wide range of traffic patterns, yet practical to be implemented in hardware. Based on the Static Round-Robin scheduling technique, we propose the SRRD cell dispatching algorithm and its variants for Clos-network switches in this paper. Our algorithms are based on the request-grant-accept (RGA) handshaking scheme, which can be implemented using simple distributed arbiters at the input and output of the Clos-network. The intuition behind our SRRD schemes is to desynchronize the...
This dissertation deals with the design of scheduling algorithms for high-speed switches. The analys...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...
The Clos-network is widely recognized as a scalable architecture for high-performance switches and r...
The Clos-network is widely recognized as a scalable architecture for high-performance switches and r...
A Clos-network switch architecture is attractive because of its scalability. Previously proposed imp...
Abstract—Clos networks provide the theoretically opti-mal solution to build high-radix switches. Dyn...
High-performance input-queued switches require highspeed scheduling algorithms while maintaining goo...
Abstract — The scalability of Clos-network switches make them an alternative to single-stages switch...
F Clos networks provide the theoretically optimal solution to build high-radix switches. This paper ...
This paper is devoted to evaluating the performance of Space-Memory-Memory (SMM) Clos-network switch...
Abstract – In this paper new packet dispatching schemes for efficient support of the uniform as well...
A Clos-network architecture is an attractive alternative for constructing scalable packet switches b...
In this paper, we extend our previous work of StablePlus, a stable scheduling algorithm for single-s...
Abstract. To provide stringent service guarantees such as latency and backlog bounds for input-buffe...
This dissertation deals with the design of scheduling algorithms for high-speed switches. The analys...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...
The Clos-network is widely recognized as a scalable architecture for high-performance switches and r...
The Clos-network is widely recognized as a scalable architecture for high-performance switches and r...
A Clos-network switch architecture is attractive because of its scalability. Previously proposed imp...
Abstract—Clos networks provide the theoretically opti-mal solution to build high-radix switches. Dyn...
High-performance input-queued switches require highspeed scheduling algorithms while maintaining goo...
Abstract — The scalability of Clos-network switches make them an alternative to single-stages switch...
F Clos networks provide the theoretically optimal solution to build high-radix switches. This paper ...
This paper is devoted to evaluating the performance of Space-Memory-Memory (SMM) Clos-network switch...
Abstract – In this paper new packet dispatching schemes for efficient support of the uniform as well...
A Clos-network architecture is an attractive alternative for constructing scalable packet switches b...
In this paper, we extend our previous work of StablePlus, a stable scheduling algorithm for single-s...
Abstract. To provide stringent service guarantees such as latency and backlog bounds for input-buffe...
This dissertation deals with the design of scheduling algorithms for high-speed switches. The analys...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...
Single-stage input-queued (IQ) switches are attractive for implementation of high performance router...