A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is proposed and experimentally demonstrated for the first time. The self-alignment between the bottom-and top-gates is realized with one backside-illuminated photolithographic step; and that between the source/drain regions and the two gates is formed by both argon plasma treatment and hydrogen doping. The resulting overlap between the gate and source/drain regions is about 0.3 m. Excellent symmetry between bidirectional transfer characteristics in the fabricated SADG TFTs is observed. Moreover, the dynamic threshold voltage operation is well demonstrated, and the driving capability, electrical stress effects under tied and separate gate biases are...
A self aligned electrically separable double gate MOS transistor technology was demonstrated. Reason...
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is pro...
In this work we present the impact of buffer layers deposited by various techniques such as plasma e...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is pro...
© 2015 Society for Information Display. We report a dual-gate (DG) self-aligned (SA) a-IGZO TFT pro...
In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demon...
In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) tech...
In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO4 and fabrica...
In this paper, a novel self-aligned double-gate (SLambdaDG) TFT technology is proposed and experimen...
In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (...
A double-gate (DG) a-IGZO TFT with separate bottom-gate and top-gate is fabricated and electrically ...
A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film trans...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
A self aligned electrically separable double gate MOS transistor technology was demonstrated. Reason...
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is pro...
In this work we present the impact of buffer layers deposited by various techniques such as plasma e...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is pro...
© 2015 Society for Information Display. We report a dual-gate (DG) self-aligned (SA) a-IGZO TFT pro...
In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demon...
In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) tech...
In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO4 and fabrica...
In this paper, a novel self-aligned double-gate (SLambdaDG) TFT technology is proposed and experimen...
In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (...
A double-gate (DG) a-IGZO TFT with separate bottom-gate and top-gate is fabricated and electrically ...
A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film trans...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
A self aligned electrically separable double gate MOS transistor technology was demonstrated. Reason...
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is pro...
In this work we present the impact of buffer layers deposited by various techniques such as plasma e...