In this work, we propose an application specific routing algorithm to reduce the hot-spot temperature for Network-on-Chip (NoC). Using the traffic information of applications, we develop a routing scheme which can achieve a higher adaptivity than the generic ones and at the same time distribute the traffic more uniformity. A set of deadlock-free admissible paths for all the communications is first obtained. To reduce the hot-spot temperature, we find the optimal distribution ratio of the communication traffic among the set of candidate paths. The problem of finding this optimal distribution ratio is formulated as a linear programming (LP) problem and is solved offline. A router microarchitecture which supports our ratio-based selection poli...
Abstract: The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the func...
In this paper, we present a routing algorithm that combines the shortest path routing and adaptive r...
Since the three-dimensional Network on Chip (3D NoC) uses through-silicon via technology to connect ...
As number of components on the semi-conductor industry is growing at a healthy rate, results in an i...
Due to the tier architecture of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the...
Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to th...
Ensuring thermal-uniformity in an integrated circuit chip is very essential for its correct operatio...
3D Network-on-Chip NoC based systems have severe thermal problems due to the stacking of dies and di...
In this paper, a routing model for minimizing hot spots in the network on chip (NoC) is presented. T...
Communication contention and thermal susceptibility are two potential issues in optical network-on-c...
In this paper, we present the Immediate Neighbourhood Temperature (INT) routing algorithm which bala...
This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as w...
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of Sys...
The final publication is available at Springer via http://dx.doi.org/10.1007/s10766-010-0159-9Networ...
Due to the constraints on VLSI scaling and reliability of chips, future processor and system-on-chip...
Abstract: The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the func...
In this paper, we present a routing algorithm that combines the shortest path routing and adaptive r...
Since the three-dimensional Network on Chip (3D NoC) uses through-silicon via technology to connect ...
As number of components on the semi-conductor industry is growing at a healthy rate, results in an i...
Due to the tier architecture of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the...
Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to th...
Ensuring thermal-uniformity in an integrated circuit chip is very essential for its correct operatio...
3D Network-on-Chip NoC based systems have severe thermal problems due to the stacking of dies and di...
In this paper, a routing model for minimizing hot spots in the network on chip (NoC) is presented. T...
Communication contention and thermal susceptibility are two potential issues in optical network-on-c...
In this paper, we present the Immediate Neighbourhood Temperature (INT) routing algorithm which bala...
This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as w...
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of Sys...
The final publication is available at Springer via http://dx.doi.org/10.1007/s10766-010-0159-9Networ...
Due to the constraints on VLSI scaling and reliability of chips, future processor and system-on-chip...
Abstract: The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the func...
In this paper, we present a routing algorithm that combines the shortest path routing and adaptive r...
Since the three-dimensional Network on Chip (3D NoC) uses through-silicon via technology to connect ...