Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs

Uniformities of carbon nanotube diameters and nanoarray pitch values of all the transistors across a chip are required to enable low cost very large scale integration (VLSI) with the carbon nanotube technology. Nanotube diameter and nanoarray pitch are concurrently optimized and unified in this paper with two different substrate bias voltages considering a wide range of p-channel transistor sizes. A performance and density metric is evaluated to identify the optimum p-type device profiles suitable for very large scale integration with a 16nm carbon nanotube transistor technology. © 2011 IEEE