Reconfigurable CMOS receiver front-end for software-defined radios

In the past decades, wireless industry has experienced fast growth. Software-defined-radio (SDR) concepts have received much research interest as this would enable a device to be reconfigurable to different standards based on availability and user needs. A SDR-enabled receiver-front-end (RFE) should be programmable to cover an ultra-wide frequency range and to handle different system specifications without degrading the performance as compared to designs for dedicated standards. In this dissertation, techniques are proposed to overcome the design challenges in implementing such an SDR RFE. Direct-conversion receivers employing passive current-driven mixer is suitable for SDR applications due to its superior 1/f noise and linearity. However, in this architecture, input transconductance has to be large to provide sufficient gain and to reduce noise. A transformer-based current-gain-boost technique is proposed. With a transformer as the interface between the LNA and the passive mixer, additional current gains of NQ time and N time (where N is the transformer turn-ratio and Q is the quality factor of transformer resonator) can be achieved for narrow-band and wide-band RFEs, respectively. Two RFEs are designed in a 0.13μm CMOS. The first dual-band low-noise RFE measures NF of 2.5dB and 3.5dB and voltage gain of 20.7dB and 17dB at 1.7GHz and 3.8GHz, respectively. The respective additional current gains at the low-band and the high-band are measured to be 9dB and 5.5dB. The second wide-band high-linearity RFE achieves 0dBm IIP3 with 4dB NF and 13dB voltage gain from 2GHz to 5GHz. while achieving an addition current gain of 2.9dB. Another critical sub-system for SDR RFE is an all-digital frequency synthesizer (ADFS). Implementing the ADFS with sufficient phase noise performance for wireless applications requires a time-to-digital converter (TDC) to have gate delay below 5ps, which is non-trivial. A 2nd-order noise-shaping TDC based on a two-stage gated ring oscillator (GRO) is proposed that relaxes the gate delay to more than 60ps without any calibration. Implemented in 65nm CMOS and sampled at 50Msps, the prototype measures 2nd-order noise-shaping with SNDR of 31.7dB in a 1MHz bandwidth. The SNDR is improved by 8.5dB as compared to the 1st-order noise-shaping. By embedding the TDC into a fully-integrated phase-locked loop, the noise-shaped quantization noise is being filtered by the loop filter. The ADFS prototype measures phase noise of -100dBc/Hz in-band and -145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V and occupying 1mm2. Finally, a 900MHz to 5.8GHz SDR RFE integrating the ADFS is proposed and demonstrated. The RFE includes a dual-band matched LNA, a 3-coil switchable transformer, a harmonic-rejection mixer (900MHz to 2GHz), an IQ mixer (2GHz to 5.8GHz), and a common-gate current buffer with regulated opamp. The mixer is designed to be reconfigurable as a harmonic-rejection (HR) mixer from 900MHz to 2GHz or as a single-sideband (SB) mixer from 2GHz to 5.8GHz. To maximize the HR and SB ratios, an automatic LO phase-error detection and calibration circuitry is also embedded. Fabricated in 65nm CMOS, the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6 dBm and -12.8dBm, 3rd-order HRR of 81dB, 5th-order HRR of 70dB while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2