Design and implementation of analog continuous-time min-sum iterative decoders

IN THIS THESIS, the concept of analog decoding as a power-saving implementation alternative to the traditional digital decoding is introduced. The advantages and disadvantages of analog decoding in compare to digital decoding are discussed. An early-stopping scheme and its potential implementation for analog decoders are proposed to further reduce power. Hardware issues on analog decoder design are discussed in details. A complete system at the circuit level of an analog continuous-time min-sum iterative decoder for an (8, 4) extended Hamming Code is proposed, designed, implemented, and fabricated. The decoder system consists of three main blocks: the input interface, the processor, and the output interface. The input interface transforms serial-input voltages into currents, performs current-mode sample-and-hold, and performs serial-to-parallel conversion. The processor receives input currents and performs iterative min-sum decoding. The output interface implements the early-stopping scheme and prepares the digital and analog output signals for the next stage, which is usually a digital signal processing unit. Dedicated circuit building blocks include a high-speed transconductance amplifier, a high-speed current-mode sample-and-hold, a peaking current source, a sign-and-magnitude conversion circuit, and an early-stopping circuit. Simulation results demonstrate the power-saving ability of the decoder. A brief conclusion is drawn and future prospects of analog decoding are discussed