BLE Transceiver/4G Mobile PLL for Wireless Applications

The Internet of Things (IoT) and cellular (mobile) systems are the most promising technologies of the next Fifth Generation (5G) of the mobile broadband network. The radio technological revolution for wireless communications has already begun. In the past, IoT wireless communications have been used in many industries, and a variety of new applications have been developed. As a result, the next-generation wireless technology, popularly known as 5G, promises to deliver new levels of capability and efficiency by supporting a diverse range of future applications, which can change the way we live, work, and communicate with each other. Based on the future 5G applications, this thesis is composed of 5 parts. The first objective of this thesis is to introduce the demands placed on monolithic local oscillators (LO), realized as RF phase-locked loops (PLLs), which are particularly exacting, especially with regard to their integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLL has become a challenging task. For instance, narrow bandwidth systems, such as the GSM of 2G and the enhanced data rate for the WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand particularly low in-band (IB) PN in a mobile cellular system. However, there has arisen a new class of operation for RF oscillators and 2-way parallelism of TDC with PVT stabilization to fill the performance/power gap in the ultra-high figure of merit (FoM) and ultra-low phase noise space. The proposed oscillator and TDC should also be implemented as the heart of a PLL system to demonstrate their superiority in a real implementation. The second objective of this thesis is to introduce an all-digital PLL that employs a digitally controlled oscillator (DCO) with switching current sources to reduce the supply voltage and power without sacrificing its phase noise and start-up margins. The DCO also reduces its 1/f noise, allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier (PA) integrates its matching network while operating in class E/F2 to maximally enhance its efficiency. The transmitter is realized in 28-nm CMOS and satisfies all metal density and other manufacturing rules. Another system-level approach is to develop the first ever fully discrete-time superheterodyne receiver for IoT applications, such as Bluetooth low-energy (BLE). It exploits the fast switching speed and low internal capacitances of deep-nanoscale CMOS devices to realize a high intermediate-frequency (IF) architecture based on switchedcapacitor- based charge-domain bandpass filtering. The power consumption is minimized by aggressively reducing the size of the MOS devices and judiciously applying a sampling-rate decimation. The resultant increase in flicker noise is mitigated by placing the IF frequency beyond the flicker corner frequency. Likewise, the decimation-induced aliasing is mitigated by DT filtering of preceding stages. To improve the power efficiency of a Bluetooth low energy transceiver by exploiting a novel digitally controlled oscillator, a class E/F2 switched-mode PA and a new discrete-time (DT) receiver (RX) are adapted to achieve high out-of-band linearity, low noise and low power consumption. In addition, an integrated on-chip matching network serves both the PA and LNTA, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The third objective of this thesis is to introduce an ultra-low voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply. While its DCO runs directly at 0.5 V, an internal switched-capacitor DC–DC converter ‘doubles’ the supply voltage to all the digital circuitry and particularly regulates the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise across process, voltage and temperature (PVT) variation. Moreover, the impact of voltage supply scaling on the power consumption and performance of a discrete-time (DT) superheterodyne receiver (RX) for IoT applications and realized in deep nanoscale CMOS using inverter-based gm and switched capacitors has been studied. The power supply is partitioned into three separate domains: RF, IF processing, and clocking, which allows them to be independently regulated to assess their respective impacts. The DT-RX maintains its functionality, albeit with some acceptable loss of performance, when the core supplies are varied by as much as an octave, i.e. from the nominal 1.1V down to 0.55 V. The DT-RX IC is then connected to a switched-capacitor based voltage doubler array on a companion IC die such that the DT-RX can be powered at the octave range of 0.275–0.55V from an energy harvester. The sensitivity at the doubler’s 0.275/0.55V input is -85/-95dBm while consuming 1.0/2.4mW. The fourth objective of this thesis is to introduce a sub-GHz transmitter (TX) with a physically merged DCO and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save c. 50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the 2nd harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11dBm output with <-55 dBc second harmonic (HD2). The fifth objective of this thesis is to improve the power efficiency and frequency range of a dual-frequency-band radar system by exploiting a third-harmonic boosting DCO simultaneously generating 22.5–28GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar and medium/long range radar requirements