Hazard-free programmable packet processor and its application

In switches and routers, packet processing has been performed in two methods: Hard wired finite state machines or packet processor. The finte-state machine approach is fast and simple, but lack of the programmability. The packet processor approach is expensive and slow, but highly programmable. It makes further changes easier to be introduced later. Each has its role to play. Many applications traditionally done by a finite state machine also demand some flexibility against future changes. Because their low complexity, it is an unacceptable overkill to replace them with packet processors. In this thesis, we proposed a packet processor which is fast and with very low complexity. They can replace traditional finite state machines with the feature of the programmability. Based on this new type of embedded programmable packet processor, an IO port processor is designed as an application. Command word mechanism is used to perform the communication tasks among the blocks. The prefetch scheme of the computer architecture has been implanted to the Buffer Management Unit of the IO port processor design. Finally, as an example, a specific traffic of the CSIX standard is tested. Simulation result is satisfying and promising