A digital VLSI design of an IP port processor (in the AAL5) implementing multiple linked-list queue Management

The Internet Protocol (IP) is a popular conventional standard in the computer communications networking industry. Connectionless IP is widely utilized for non-real-time services such as intemet-browsing and emails. With suitable network layers such as the TCP (Transmission Control Protocol), connection-oriented services can also be provided. However, nowadays due to the enormous demand for extremely high networking speed, the ordinary TCP/IP networks may not be able to cope with these requirements in the future. The ATM (Asynchronous Transfer Mode) - the most popular broadband networking standard, on the other hand, is a much better candidate for the protocols of connection-oriented services. In order to transmit IP packets in the ATM networks, some standards like the AALS (ATM Adaptation Layer type 5) were developed to make the IP over ATM possible. In this thesis, a novel VLSI design of a 100 MHz port processor which handles IP traffic in the AALS is investigated. Apart from carrying out the normal IP and AALS functions, a special way of packet discarding with the queue management in the linked-list approach is also implemented which will be discussed in great details. This port processor is integrated with another port processor which deals with real-time ATM traffic in a single VLSI chip. In this chip, the input and output interfaces are shared between both port processors. This chip is one of the cores in the project A/I Net which aims at an efficient integration of the processing of both ATM and IP traffic in one network to eliminate the deficiencies of a stand-alone ATM or IP network