Power optimization of embedded controller

In order to successfully introduce a new portable electronic product (like pager, mobile phone and PDA) in today's market, the product requires not only innovative and creative functionality, but also shorter design process cycle time and lower power consumption. To optimize power consumption, trade-off between power, area and timing of a design should be explored in the earliest stage before the actual implementation. In this thesis work, we studied how to obtain low power consumption for a microcontroller design using a high-level design automation framework. The framework allows the designer to start a design from its behavioral specification, through an architectural level design tool to produce various architectures of the design. An automatic synthesis, power and functional simulation processes will then be carried out. Finally the power, area and timing of different architectures are compared in both RT- and gate level. Several architectural level power optimization techniques were studied in our microcontroller design. Experimental results show that as much as 35% of average power reduction can be achieved when compared with the original architecture. The results also show the power consumption distribution for each functional unit of the microcontroller design. We found that the Controller Unit, which mainly consists of a Finite State Machine (FSM), consumed a significant portion of power than the other units. Therefore, we carried out an independent study on reducing the power consumption of FSM by clock gating technique. By pre-computing and identihing self-loop events in a FSM, we can disable the clock signal to prevent unnecessary switching activities for the combinational logic in the FSM. To eflectively apply the clock gating technique, the probability of self-loop in a FSM should be maximized. We propose a technique to decompose a FSM into two sub-FSMs, which resulted in increasing the self-loop probability. A set of experiments for the MCNC91 benchmarks were carried out, the results show that some FSMs have increase an order of magnitude or more of self-loop probability, with 20 to 40 percent area overhead. Finally we performed power estimation for gated clock FSM. By comparing the results between the original FSM and the decomposed FSM, we can see an average of 40% power saving by the gated clock decomposed FSMs