On-chip planar spiral inductor induced substrate effects on radio frequency integrated circuits in CMOS technology

Recently, we have witnessed an increasing interest in integrating inductors in analog RF ICs to attain higher integration and thus lower the production cost. Thanks to the great advances in the multi-layer metal processing and the higher frequency requirement, we have been able to integrate inductors of reasonable qualities. An unfortunate by-product that comes along with a higher integration is a higher susceptibility to interference, such interference is substrate noise. In this thesis, experimental data and simulation results for inductor-induced substrate effects on RF ICs in CMOS technology will be presented. A test chip has been fabricated in 0.8um CMOS n-well technology to study the inductor-induced noise with verification by a 3D simulation. A design example reveals that inductor-induced noise can be a major obstacle in RF circuit integration. Various schemes in reducing inductor-induced substrate effects were also investigated. Distance separation is found to be less effective in reducing noise in the epi process. The effectiveness of various guard rings configurations in reducing noise coupling were studied. The trade-off between noise coupling and self-inductance was addressed. Next, noise coupling from conventional and hollow inductors via the substrate to P+ diffusion with and without guard rings were examined. N-well substrate bias effects on inductor was also examined in this thei