Multi-precision reconfigurable multiplier for low power application

Multiplication is one of the fundamental operations used in most arithmetic computing systems. Multiplier design is becoming more important since the performance of multiplication is crucial for modern applications such as multimedia and signal processing systems, which depend on the execution of large numbers of multiplications. People have already done a great amount of work on two major design goals, namely, speed performance and design layout area. Recently, more efforts have been spent on low power design and flexible design that can adopt different computing scenarios. At algorithm and architecture level, this thesis addresses multiplier design on reconfigurable operating and power consumption. We have analyzed and implemented many existing multiplier coding schemes in our multiplier design. Optimization of multiplier recoding has also been investigated. Accordingly we have combined Radix-4 recoding scheme with reconfigurable control structures in effort to improve performance. To achieve multi-precision and reconfigurable design, we have proposed new multiplier schemes that have flexibility in adapting operands in different word length. They inherently address power issue by different operating modes. Experiments in both FPGA board and VLSI standard cell design have been done independently. We have used Alcatel CMOS 0.35um standard cell library to do the simulation, power consumption and delay performance are analyzed in detail. To deal with low-power application, we introduced block-wise shutdown to our reconfigurable multiplier design. Voltage scaling techniques have also been investigated and applied for low power design and achieving optimal operating mode. They can greatly reduce the power consumption while still keep the design regular and scalable. Our work shows that the designs are both scalable and reconfigurable for application that needs the adjustments in trade-off of power consumption and precision requirement