CMOS-compatible zero-mask one time programmable (OTP) memory design

One time programmable memory (OTP) is one type of nonvolatile memory (NVM). The most attractive feature of OTP is low cost and simple process. Existing NVMs such as the FLASH, aside from having technology scaling limitations, require additional masks and process modifications to CMOS that makes the cost increase. Other types of NVMs such as the antifuses (AF) do not have limitation problem and the cost of fabrication of it is lower than FLASH. However, the mainstream AFs still require three masks to the standard CMOS. OTP has found many applications in trimming, storage element in RFID and IP protection. In particular, CMOS compatible zero-additional-mask approach has been the most popular method to implement OTP memories. In this thesis, a diode based OTP memory technology using the breakdown of PN diode as the OTP element has been developed. The memory cell and array configuration, as well as charge pump that can be readily integrated in conventional CMOS. In Chapter 2, In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. The electrical characteristic of the polysilicon diodes have been studied. The design of the polysilicon diode and the silicon substrate diodes as memory elements of the diode based OTP memory is discussed in this thesis. Different memory cells were fabricated in the standard 0.18-μm CMOS technology to verify the functionality of the design. In Chapter 3, the maximum output voltage of the charge pump circuit is limited by the breakdown voltage between the undesired silicon substrate diode between the N-type drain and the grounded P-type substrate. The output voltage of charge pump which is fully implemented by polysilicon diodes can be larger than the breakdown voltage of the undesired silicon substrate diode. However, the pumping efficiency of the charge pump is very low because of the diode voltage drop of the polysilicon diodes. To improve the pumping efficiency of an ultra high voltage charge pump, the gate control circuit is implemented in my charge pump circuit. A off chip capacitor charge pump which is implemented by polysilicon diodes and gate control circuits is fabricated in the standard 0.18-μm CMOS process to verify the idea of the design. Finally, in Chapter 4 the thesis draws the conclusions on the study of diode based OTP memory