An efficient structural approach to board interconnect diagnosis

This paper presents a new structural approach for diagnosing board interconnects using boundary-scan. While existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in CMOS circuit environment. The diagnostic test set is generated based on graph theoretic technique and the adjacency fault model is adopted. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing and confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan resting