Design of experiment (DoE) study on effects of various geometric parameters on copper diffusion in through silicon vias (TSVs)

For 3D stacked flip chip packages, through silicon vias (TSVs) are employed as vertical interconnection within the silicon die. The TSVs are usually plugged with Cu using an electro-plating process. To prevent Cu diffusion, improve the Cu adhesion and provide electrical insulation, the interfacial multilayers must be deposited on the TSV sidewall. In this paper, the Cu-to-Si diffusion in TSVs is investigated. The Cu diffusion behaviors are characterized by depth profiling analysis using secondary ion mass spectrometry (SIMS). The roles of interfacial multilayers of TSVs are studied and compared as well. Regarding Cu-to-Si diffusion, the effects of Si surface roughness, insulation layer, barrier layer and the Cu source supply are investigated. Experimental results show that the SiO2 layer not only serves for electrical insulation, but also helps to maintain the integrity of the TaN barrier layer and to prevent further diffusion of Cu into the silicon. From a surface roughness comparative study, the experimental results show that a rougher silicon surface may promote Cu diffusion depth and subsequently will impose a higher threat on the IC devices. Therefore, a smooth surface is preferred for the deposition of interfacial multilayers of the sidewall of TSVs. The TaN barrier layer in the interfacial multilayer structure on a smooth silicon substrate can effectively prevent Cu diffusion at an annealing temperature lower than 300 degrees C. However, when the annealing temperature is raised to 300 degrees C or above, the barrier layer tends to breakdown and the Cu element will surpass the TaN layer. It is also identified that the Cu layer thickness may affect the Cu diffusion depth. In general, a thicker Cu layer will promote the Cu diffusion depth. This effect reveals that the Cu diffusion in TSVs for 3D packaging should be different from that in the Cu damascene structure for on-chip interconnection. Furthermore, Cu3Si is found when the barrier layer fails. To effectively control the copper diffusion in TSVs, the thickness of different layers in the interfacial multilayer structure should be optimized. An influential rank study of different layers by design of experiment (DOE) is presented in this paper. The results indicate that Si roughness is the most important impact factor. Therefore, a smaller Si roughness is preferred. Because the Si roughness is smaller for smaller TSVs by DRIE, the TSVs size should be balanced between the Cu diffusion and TSVs fabrication feasibility. Secondly, SiO2 is more important than TaN within their factor levels. Due to the low Cost Of SiO2, a thick SiO2 layer should be adopted rather than a thick TaN layer. Furthermore, thicker Cu. film thickness will increase Cu diffusion depth and impose more threats to silicon devices