Architecture of a low storage digital pixel sensor array with an on-line block-based compression

In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3BPP