A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

We study the implementation of data- flow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We focus on the runtime environment assuming global static scheduling, time-triggered and non-preemptive execution of tasks. Our contributions include (i) a technique to implement SCADE applications compli- ant with execution models inspired by PREMs (PRe- dictable Execution Models), (ii) an exhaustive com- parison of three execution models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.