Low-precision floating-point arithmetic can be simulated via software by executing each arithmetic operation in hardware and rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing algorithms are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library that offers efficie...
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addi...
(eng) We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that i...
Shrinking feature sizes gives more headroom for designers to extend the functionality of microproces...
One can simulate low-precision floating-point arithmetic via software by executing each arithmetic o...
The half precision (fp16) floating-point format, defined in the 2008 revision of the IEEE standard f...
Floating-point numbers have an intuitive meaning when it comes to physics-based numerical computatio...
International audienceThis paper presents a multiple-precision binary floating-point library, writte...
Abstract. Most mathematical formulae are defined in terms of operations on real numbers, but compute...
International audienceFloating-Point (FP) units in processors are generally limited to supporting a ...
Floating-point arithmetic is considered an esotoric subject by many people. This is rather surprisin...
We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that is not ...
Floating-point arithmetic is considered an esotoric subject by many people. This is rather surprisin...
We demonstrate tools and methods for proofs about the correctness and numerical accuracy of C progra...
International audienceOptimizing compilers for high performance computing only support IEEE 754 floa...
International audienceFloating-point arithmetic is known to be tricky: roundings, formats, exception...
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addi...
(eng) We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that i...
Shrinking feature sizes gives more headroom for designers to extend the functionality of microproces...
One can simulate low-precision floating-point arithmetic via software by executing each arithmetic o...
The half precision (fp16) floating-point format, defined in the 2008 revision of the IEEE standard f...
Floating-point numbers have an intuitive meaning when it comes to physics-based numerical computatio...
International audienceThis paper presents a multiple-precision binary floating-point library, writte...
Abstract. Most mathematical formulae are defined in terms of operations on real numbers, but compute...
International audienceFloating-Point (FP) units in processors are generally limited to supporting a ...
Floating-point arithmetic is considered an esotoric subject by many people. This is rather surprisin...
We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that is not ...
Floating-point arithmetic is considered an esotoric subject by many people. This is rather surprisin...
We demonstrate tools and methods for proofs about the correctness and numerical accuracy of C progra...
International audienceOptimizing compilers for high performance computing only support IEEE 754 floa...
International audienceFloating-point arithmetic is known to be tricky: roundings, formats, exception...
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addi...
(eng) We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that i...
Shrinking feature sizes gives more headroom for designers to extend the functionality of microproces...