A message-driven VLSI architecture for parallel object-oriented systems

This Thesis investigates a "transputer-like" microprocessor architecture optimised for parallel object-oriented systems. This investigation comprises: specification of a virtual, parallel, object-oriented machine; design of a microprocessor architecture; simulation studies of the microprocessor; and implementation of a 2-micron CMOS microchip prototype. Object-oriented software systems have now secured wide adoption within industry. However, few computers provide hardware structures optimised for object support or take advantage of object-based parallelism. The aim of this work is to address this problem, designing a parallel architecture based on a network of custom VLSI microprocessors, with specialised object-oriented hardware support. A parallel virtual machine, derived from an abstract object-oriented computing model, was the basis to develop the whole architecture. Object-oriented languages and machines were studied to outline this abstract computing model and the underlying architecture. A microprocessor-based system was designed to support the virtual machine. The resulting system, called BROOM, is a distributed architecture, supporting intrinsic object-based parallelism. Objects are embodied by the processing nodes and served in a non-preemptive multitasking schedule. Messages are the key activators for this scheduling scheme. They are processed as atomic instructions, decoded and executed by three pipelined units in the microprocessor node. A simulator was written in C++ to investigate the microprocessor operation, assessing the feasibility of the proposed computing model. The simulator emphasis is on instructions and operations designed for object and message support, which were modelled under a message based timescale. A microchip prototype of the BROOM node architecture was implemented in 2-micron CMOS. Message-driven computation is provided by three independent PLA based controllers, organised in a high level pipeline. Objects, messages and methods are supported by on-chip static memory caches. Methods are executed on a 32 bit stack-oriented datapath, controlled by single-cycle, eight bit instructions. In summary, the prime contribution of this thesis is an object-oriented machine supporting high object-based parallelism and a special object-oriented instruction set. This is done through a distributed, multinode architecture and a high level pipeline organisation of the node processor